It is conventional for high-speed data communications systems to transmit data without any additional timing references. Receivers in such embedded clock systems include a clock and data recovery (CDR) circuit that retrieves the clock responsive to the binary transitions in the received data. For this reason, embedded clock systems typically encode the data to prevent long series of consecutive binary ones or zeroes so as to ensure there are sufficient binary transitions to enable the CDR circuit to retrieve the clock.
To perform the clock retrieval, CDR circuits typically use some form of a phase detector circuit. Although phase detectors allow the CDR circuit to detect the binary transitions, such detections without frequency detection can be problematic. In particular, the CDR circuit may lock onto an incorrect frequency instead of the desired clock frequency, such as due to the presence of jitter. To prevent such conditions, CDR circuits with frequency detectors have been developed. The frequency detector enables a CDR circuit to distinguish the offset between the clock rate and the data rate so that the clock is not synchronized incorrectly.
However, conventional CDR circuits with frequency detection are complex and power hungry, thereby increasing the costs of manufacturing and limiting battery life in mobile systems that incorporate such conventional CDR circuits. Accordingly, there is a need in the art for CDR circuit designs with frequency detection with reduced complexity and power consumption.